The present invention relates to a synchronizing circuit and a bias voltage generation circuit for the phase locked loop.
A phase locked loop (PLL) and a delay locked loop (DLL) are representative examples of a feedback system. In a synchronous semiconductor memory device, the feedback system transfers data to/from external devices with the help of an internal clock signal that is locked in synchronization with an external clock signal input from an external device such as a memory controller. Therefore, the synchronization of the data transfer with the reference clock signal is very important for a stable data transfer between the semiconductor memory device and the memory controller.
A typical PLL feedback system includes a phase frequency detector, a charge pump, a loop filter and a voltage-controlled oscillator, to change a frequency according to a clock signal input to a PLL system. The phase frequency detector detects a phase difference between an input clock and a return clock to generate an up signal UP or a down signal DN according to the phase difference. The charge pump outputs current proportional to the up and down signals. The loop filter smoothes the current to output a voltage. The voltage-controlled oscillator receives the voltage to output a frequency.
The feedback system is used in a variety of digital circuits such as a semiconductor memory device. The feedback system is composed of an NMOS transistor and a PMOS transistor owing to restrictions of capacity, volume, and the like. Therefore, the feedback system requires an NMOS control voltage (hereinafter, referred to as “N-bias voltage”) for the NMOS transistor, and a PMOS control voltage (hereinafter, referred to as “P-bias voltage”) for the PMOS transistor.
Accordingly, nowadays, the PLL system includes a bias voltage generation circuit generating a control voltage for a MOS transistor.
FIG. 1 is a circuit diagram of a bias voltage generation circuit for generating a bias voltage of an NMOS transistor used in a conventional PLL system.
Referring to FIG. 1, the conventional bias voltage generation circuit includes a bias unit 10, an operational (OP) amplification unit 20, and an N-bias voltage output unit 30. The bias unit 10 receives a bias control voltage to generate a DC current of the OP amplification unit. The OP amplification unit 20 differential-amplifies a control voltage VCTRL received from a charge pump (not shown). The N-bias voltage output unit 30 includes a capacitor CLOAD for adjusting phase margins of the OP amplification unit 20 and a replica cell of a voltage-controlled oscillator (VCO).
The bias unit 10 includes a PMOS transistor MP1 and two NMOS transistors MN1 and MN2 connected in series between a supply voltage VDD and a ground voltage. The PMOS transistor MP1 has a source connected to the supply voltage VDD, and a drain and a gate connected to a common node. The NMOS transistor MN2 has a drain connected to the drain of the PMOS transistor MP1, a gate configured to receive an enable signal, and a source connected to a drain of the NMOS transistor MN1. The NMOS transistor MN1 has the drain connected to the source of the NMOS transistor MN2, a gate configured to receive a bias control voltage VEXT, and a source connected to the ground voltage.
The OP amplification unit 20 differentially amplifies a control voltage VCTRL in response to a DC current received from the bias unit 10. The OP amplification unit 20 includes a PMOS transistor MP2. The PMOS transistor MP2 has a source connected to a supply voltage, a gate connected to the gate of the PMOS transistor MP1, and a drain connected to PMOS transistors MP3 and MP4.
The PMOS transistor MP3 has a source connected to the drain of the PMOS transistor MP2, a gate configured to receive a control voltage VCTRL generated by a charge pump (not shown), and a drain connected to a drain of the NMOS transistor MN3. The NMOS transistor MN3 has the drain connected to the drain of the PMOS transistor MP3, and a source connected to a ground voltage. The PMOS transistor MP4 has a source connected to the drain of the PMOS transistor MP2, a gate connected to the output unit 30, and a drain connected to a drain of an NMOS transistor MN4. The NMOS transistor MN4 has a source connected to a ground voltage, and a drain and a gate connected to each other. Gates of the NMOS transistors MN3 and MN4 are interconnected. A node connecting the PMOS transistor MP3 and the NMOS transistor MN3 is connected to an N-bias output terminal of the output unit 30.
The output unit 30 includes a capacitor CLOAD for adjusting phase margins of the OP amplification unit 20 and a VCO replica cell (not shown). The capacitor CLOAD is connected to the output terminal outputting a voltage differentially amplified by the OP amplification unit 20. The output unit 30 also includes a circuit for controlling a feedback signal according to an output of the OP amplification unit 20.
In other words, the output unit 30 includes PMOS transistors MP5 and MP6. The PMOS transistor MP5 has a gate configured to receive the control voltage VCTRL from the charge pump (not shown), and a source connected to the supply voltage. The PMOS transistor MP5 also has a drain connected to a common node connecting a gate and a drain of the PMOS transistor MP6. A source of the PMOS transistor MP6 is connected to a supply voltage. The common node is connected to the gate of the PMOS transistor MP4 in the OP amplification unit 20 to form a feedback path from the output unit 30 to the OP amplification unit 20.
Three NMOS transistors MN5, MN6 and MN7 are connected between the common node and a ground voltage. A gate of the NMOS transistor MN5 is connected to a supply voltage, a gate of the NMOS transistor MN6 is configured to receive an enable signal, and a gate of the NMOS transistor MN7 is configured to receive an output of the OP amplification unit 20.
A method for generating an N-bias voltage by the conventional bias voltage generation circuit having the above-described configuration will be described below.
Referring to FIG. 1, an MRS (not shown) applies the enable signal to the gate of the NMOS transistor MN2 in the bias unit 10 and to the gate of the NMOS transistor MN6 in the output unit 30, to enable the bias voltage generation circuit. Then, the bias control voltage VEXT is input to the gate of the NMOS transistor MN1 in the bias unit 10 so that the bias unit 10 generates a DC current to be used in the OP amplification unit 20 according to the bias control voltage level. The DC current generated by the bias unit 10 determines a current to be applied to the PMOS transistors MP3 and MP4, which constitute a differential amplifier.
As the charge pump (not shown) applies the control voltage VCTRL to a gate of the PMOS transistor MP3, the OP amplification unit 20 generates an N-bias voltage proportional to the control voltage VCTRL and outputs the N-bias voltage to the output unit 30.
The output unit 30 outputs the N-bias voltage VNCTRL generated by the OP amplification unit 20 to an outside of the N-bias generation circuit through the output terminal. The N-bias voltage is supplied to every NMOS transistor requiring the N-bias voltage in a PLL system.
The output voltage of the OP amplification unit 20 is applied to the gate of the NMOS transistor MN7 to determine a turn-on characteristic of the NMOS transistor MN7. The feedback voltage to the OP amplification unit 20 is determined depending on the turn-on characteristic of the NMOS transistor MN7. That is, the control voltage VCTRL generated by the charge pump is applied to the gate of the PMOS transistor MP5 to transfer the supply voltage through the PMOS transistor MP5. Here, the current amount is controlled by the turn-on characteristic of the NMOS transistor MN7.
In the conventional bias voltage generation circuit, a resistance REFF of the output terminal in the OP amplification unit 20 and a capacitor (load) connected to the output terminal of the output unit 30 create a pole. The pole location corresponds to a bandwidth of the bias voltage generation circuit.
However, since the PLL system uses a bias voltage generated in its bias voltage generation circuit as described above, the pole may decrease a phase margin of the PLL system.
FIG. 2 is a graph illustrating an open loop gain and a phase margin of a PLL system with an N-bias pole and those of the PLL system without the N-bias pole. Referring to FIG. 2, a zero created by a P-bias voltage generation circuit of the PLL system gradually increases a phase margin, however, a pole of the N-bias voltage generation circuit decreases the phase margin.
Consequently, because of the pole of the N-bias voltage generation circuit, the PLL system may not have a sufficient phase margin. This may decrease the stability of the PLL system, and may cause a jitter peaking due to an input clock noise and a power noise, thereby deteriorating a jitter characteristic.